This invention relates to the field of integrated circuits. More particularly, this invention relates to methods to improve hybrid orientation substrates.
It is well recognized that increasing the mobility of charge carriers in metal oxide semiconductor (MOS) transistors in integrated circuits (ICs) improves the operating speed of ICs. There are several techniques used in advanced ICs to increase the mobilities of electrons and holes in silicon n-channel MOS (NMOS) and p-channel MOS (PMOS) transistors, including orienting the silicon substrate to take advantage of the fact that carrier mobility varies depending on the orientation of the crystal lattice in the MOS transistor channel. Electrons have maximum mobility in (100)-oriented silicon when the NMOS transistor is aligned on a [110] axis, that is, when the electron movement in the NMOS transistor channel is along a [110] direction. Holes have maximum mobility in (110)-oriented silicon when the PMOS transistor is aligned on a [110] axis. To maximize the mobilities of electrons and holes in the same IC requires regions with (100)-oriented silicon and (110)-oriented silicon in the substrate, known as hybrid orientation technology (HOT). Known methods of HOT include amorphization and templated recrystallization (ATR), in which regions to be reoriented receive an amorphization ion implant, followed by a recrystallization anneal. In one variation of ATR, in which recrystallization is performed before a shallow trench isolation (STI) process, discontinuities and defects (morphology) are introduced in a region approximately 100 nanometers wide at the lateral boundaries between (100)-oriented and (110)-oriented silicon. The morphology region is not suitable for MOS transistors, proscribing conventional ATR for use in circuits requiring high transistor density, such as SRAMs or logic gates. The morphology region also imposes unacceptable limits on transistor scaling. In another variation of ATR, in which recrystallization is performed after an STI process, stable defects are introduced at the STI boundaries which require anneals over 1250° C. to be eliminated. Such anneals after STI are incompatible with maintaining dimensional integrity of the substrate required for deep submicron lithography used in the 65 nanometer technology node and more advanced nodes.